Juniper is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At Juniper Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting-edge networking chips used to build world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced chip design group, you will become an expert in building and/or validating high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex blocks where you can challenge yourself and grow. You will have a significant opportunity to interact with system design teams across geographies.

Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.

Responsibilities:

• Architect complex modules and subsystems used in high performance networking chips.

• Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.

• Implement the design using Verilog or System Verilog

• Write functional coverage/SVA to help verification catch corner case bugs.

• Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.

• Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.

• Collaborate with the Verification team to make sure your block is fully validated.

• Show leadership and provide guidance to new college-grad/junior engineers and interns.

Recommended skills

• Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 15+ years of relevant experience.

• Strong analytical/ problem solving skills.

• Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.

• Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.

• Strong coding skills in Verilog/System Verilog through previous work experience are necessary.

• Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.

• Excellent written and verbal communications skills is necessary.

• Knowledge of Perl/Python is strongly desired.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

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Minimum Salary: $142,848.00

Maximum Salary:$205,344.00

The pay range for this position is expected to be between $142,848.00 and $205,344.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position also includes medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.

If hired, employee will be in an “at-will position” and the Company reserves the right to modify base salary (as well as any other payment or compensation program) at any time, including for reasons related to individual performance, Company or individual department/team performance, and market factors.

Juniper’s pay range data is provided in accordance with local state pay transparency regulations. Juniper may post different minimum wage ranges for permanent residency petitions pursuant to US Department of Labor requirements.